FIG. 12 shows an example of a memory cell of a nonvolatile semiconductor memory device. Here, an example of a nonvolatile semiconductor memory device that is generally called a flash memory is shown.
A cell of the flash memory is constituted of one MOS field-effect transistor (FET) which has a floating gate, a control gate, a source and a drain, and is capable of retaining two types of states by storing or not storing a negative charge in the floating gate. Hereinafter, a transistor refers to a MOS field-effect transistor unless otherwise noted.
In the memory cell, the control gate is connected to a word line WL, the source is connected to a reference potential (ground) VSS, and the drain is connected to a bit line BL. When the memory cell is selected, the word line WL is raised to high electric potential, and a voltage is applied to the bit line BL. At this time, if a negative charge is stored in the floating gate, the transistor remains in an OFF state and does not pass a current. However, if the negative charge is not stored, the transistor is in an ON state and therefore passes a current of the order of ten and a few μA from the bit line BL to the reference potential VSS.
FIG. 13 shows an overall view of a nonvolatile semiconductor memory device including the memory cell. Inputted address information of plural bits can be divided into an address A1 of plural bits and an address A2 of plural bits. A memory cell array 1301 has plural memory cells MC which are two-dimensionally arranged. Each memory cell MC corresponds to the memory cell in FIG. 12 and is connected to the word line WL and the bit line BL.
A decoder 1302 decodes the address A1 and activates a predetermined word line WL to have a high electric potential. By raising one word line WL to high electric potential by the address A1, a memory cell MC connected to this word line WL is selected.
A column selecting circuit 1303 connects one of the plural bit lines BL to a data bus (line) DATA-BUS based on the address A2. In order words, the bit line BL is selected by the address A2 and connected to the data bus DATA-BUS, and eventually one memory cell MC is connected to a sense circuit 1304. The sense circuit 1304 applies a voltage to a bit line BL connected to the selected memory cell MC and detects whether or not a current can flow thereto, and outputs a result thereof as voltage information of high level or low level to an output line OUTPUT.
FIG. 14 shows a configuration example of the sense circuit 1304 in the prior art. This sense circuit is divided into preamplifier units 1401, 1402 which perform current-voltage conversion and a main amplifier unit (differential amplifier circuit) 1403 which detects a minute differential voltage between two inputs.
The preamplifier unit 1401 has the following configuration. In a p-channel MOS transistor m01, a gate is connected to an activation signal /pre-en, a source is connected to a power supply potential, and a drain is connected to a node node-D. In this description, a symbol “/” denotes logical negation. The activation signal /pre-en is activated by a low level. In an n-channel MOS transistor m02, a gate is connected to the output of an inverter x01, a source is connected to a data bus DATA-BUS, and a drain is connected to the node node-D. The input of the inverter x01 is connected to the data bus DATA-BUS. In an n-channel MOS transistor m03, a gate is connected to the activation signal /pre-en, a source is connected to the ground potential, and a drain is connected to the data bus DATA-BUS.
The preamplifier unit 1402 has the same configuration as the above-described preamplifier circuit 1401. While the preamplifier unit 1401 is connected to the data bus DATA-BUS, the preamplifier unit 1402 is connected to a reference bus (line) Reference-BUS instead. The reference bus Reference-BUS is connected to a reference memory cell. Further, while the preamplifier unit 1401 is connected to the node node-D, the preamplifier unit 1402 is connected to a node node-R instead.
The differential amplifier circuit 1403 turns to an enable state by an enable signal out-en, and then amplifies a differential voltage between two input signals of the nodes node-D and node-R and outputs it to an output line OUTPUT.
The preamplifier unit 1401 is also generally referred to as a CASCODE circuit, which varies the voltage level of the node node-D as an output according to the current flowing in the data bus DATA-BUS. As shown in FIG. 15, it is activated by a change of the activation signal /pre-en from a high level (hereinafter, denoted by H) to a low level (hereinafter, denoted by L), and first the transistors m01 and m02 are both turned on to apply a voltage to the data bus DATA-BUS. The data bus DATA-BUS is connected to the bit line BL, so that finally the voltage is also applied to the bit line BL. In this state, if the memory cell MC is in an OFF state, the electric potential of the data bus DATA-BUS rises to a threshold voltage of the inverter x01 so that the inverter x01 inverts its output from H to L, thereby turning off the transistor m02. Then, since the path for a charge to pass through no longer exists, the node node-D rises to a power supply level. On the other hand, if the memory cell MC is in an ON state, the electric potential of the data bus DATA-BUS does not rise to the threshold voltage of the inverter x01, and thus the transistor m02 is not turned off. Then, the node node-D does not rise to the power supply level and settles down to an intermediate electric potential that is determined by on-resistance ratios of the transistors m01, m02 and the transistor of the memory cell MC.
The preamplifier unit (CASCODE circuit) 1402 is connected to the reference bus Reference-BUS instead of the data bus DATA-BUS and outputs a reference potential to the node node-R. To the reference bus Reference-BUS, a reference memory cell, which is specially prepared for sensing, is connected. This reference memory cell is adjusted to pass a current that is approximately half of a current passed by the normal memory cell MC in the ON state, and also the electric potential of the node node-R is adjusted to be exactly the middle between the voltage of the node node-D at the time that the memory cell MC is in the ON state and the voltage of the node node-D at the time that the memory cell MC is in the OFF state.
In FIG. 15, voltage waveforms of the data bus DATA-BUS and the nodes node-D, node-R at this time are shown. For the voltages of the data bus DATA-BUS and the node node-D, waveforms at the time that the memory cell is OFF are shown as a data bus voltage DATA-BUS-OFF and a node voltage node-D-OFF by solid lines, and waveforms at the time that the memory cell is ON are shown as a data bus voltage DATA-BUS-ON and a node voltage node-D-ON by dotted lines.
The voltage difference between the nodes node-D and node-R is not so large. Therefore, in the sense circuit, the differential amplifier circuit 1403 which amplifies the differential voltage between them is prepared as a main amplifier. Various types of this differential amplifier circuit 1403 may exist, and they can be commonly seen in a generic semiconductor device. The differential amplifier circuit 1403 is activated by a change of the enable signal out-en from L to H and detects a voltage difference between the nodes node-D and node-R and outputs information to the output line OUTPUT.
Generally, in a sense circuit on a semiconductor device, a certain level of imbalance occurs due to manufacturing variability of constituting elements thereof. Accordingly, in order to accurately detect a differential voltage between two signals, output of a sensing result needs to be put off until a differential voltage equal to or higher than the imbalance occurs at a sense circuit input. In the case of the example in FIG. 14, activation of the differential amplifier circuit 1403 needs to be put off until an adequate differential voltage occurs between the data bus DATA-BUS and the reference bus Reference-BUS. However, a semiconductor memory device has a large total number of memory cells in one chip owing to the advance in miniaturization, and parasitic capacitances in the bit line BL and data bus DATA-BUS becomes large accordingly, so that the potential variation in the data bus DATA-BUS becomes slow. This makes the time until an adequate differential voltage occurs between the data bus DATA-BUS and the reference bus Reference-BUS become long, and thus the time until output of a sensing result becomes long. As a result, there arises a concern that an access speed from input of an address to output of data becomes slow.
In FIG. 16, enlarged voltage waveforms of the data bus DATA-BUS and waveforms of load currents to be sent to the data bus DATA-BUS are shown. A load current I-DATA-BUS-ON is a load current at the time that the memory cell is in the ON state, and the load current I-DATA-BUS-OFF is a load current at the time that the memory cell is in the OFF state. A differential voltage needed at the sense circuit input is denoted by ΔV. Since the reference bus Reference-BUS is adjusted to be an intermediate electric potential between the data bus voltage DATA-BUS-OFF at the time that the memory cell is in the OFF state and the data bus voltage DATA-BUS-ON at the time that the memory cell is in the ON state, a time for the differential voltage of the data bus DATA-BUS in both the states to be (2×ΔV) is the time when the sense circuit can produce an output.
When the preamplifier unit 1401 is activated, a large peak current appears once in the load currents I-DATA-BUS-ON, I-DATA-BUS-OFF, and the data bus voltages DATA-BUS-ON, DATA-BUS-OFF are raised at relatively high speed. However, when the data bus voltages DATA-BUS-ON, DATA-BUS-OFF come to a certain level, the load currents I-DATA-BUS-ON, I-DATA-BUS-OFF become small, and thus the rises of the data bus voltages DATA-BUS-ON, DATA-BUS-OFF become slow. Thereafter, if the memory cell is in the ON state, the load current I-DATA-BUS-ON and a cell current become balanced and thus the rise of the electric potential of the data bus DATA-BUS stops in an early stage, but if the memory cell is in the OFF state, the data bus voltage DATA-BUS-OFF continues to rise slowly. However, as it rises, the transistor m02 is turned OFF and the load current I-DATA-BUS-OFF decreases to be 0 (zero) at last, and soon the rise of the data bus voltage DATA-BUS-OFF stops. For the voltage of the reference bus Reference-BUS, the load current I-Reference-BUS becomes balanced with the reference memory cell current, and the rise of an electric potential thereof stops at approximately the middle between the data bus voltage DATA-BUS-ON at the time that the memory cell is in the ON state and the data bus voltage DATA-BUS-OFF at the time that the memory cell is in the OFF state. By such a difference in operations, the differential voltage ΔV is generated between the data bus DATA-BUS and the reference bus Reference-BUS.
The speed to generate this difference in electric potential is determined by parasitic capacitances in the data bus DATA-BUS and the bit line BL and the amount of a load current flowing into them. Even when the parasitic capacitance increases, variation of the electric potential of the data bus DATA-BUS does not become slow if the current can be increased in proportion thereto, and thus the decrease in access speed does not occur. However, a current value which generates a differential voltage in the data bus DATA-BUS is limited equal to or lower than an ON current of the memory cell. In this method, it gradually decreases as the differential voltage increases, which makes the increase of the necessary differential voltage further slower. The upper limit of a current flowing in the memory cell has a limit that is determined depending on its manufacturing process, and thus it cannot be increased easily.